The present invention relates to the fabrication of semiconductor-based devices. More particularly, the present invention relates to improved techniques for fabricating semiconductor-based devices with a metallization layer and a low-k dielectric layer.
In semiconductor IC fabrication, devices such as component transistors are formed on a semiconductor wafer or substrate, which is typically made of silicon. Metallic interconnect lines, which are etched from a metallization layer disposed above the wafer, are then employed to couple the devices together to form the desired circuit.
In an example of layer stack with a metallization layer, a dielectric layer is formed above wafer. A barrier layer may be disposed between the dielectric layer and a subsequently deposited metallization layer. A barrier layer, when provided, functions to prevent the diffusion of atoms from dielectric layer into the metallization layer.
The metallization layer typically comprises aluminum or one of the known aluminum alloys such as Al—Cu, Al—Si, or Al—Cu—Si. For convenience, the metallization layer is referred to herein as the aluminum layer or an aluminum containing layer although it should be understood that such a reference may include a layer consisting of any of the aforementioned aluminum alloys. An anti-reflective coating (ARC) layer and an overlaying photoresist (PR) layer, are then formed atop the metallization layer. The ARC layer helps prevent light (e.g., from the lithography step that patterns the photoresist) from being reflected and scattered off the surface of the metallization layer and may, in some cases, inhibit hillock growth. The photoresist layer represents a layer of conventional photoresist material, which may be patterned for etching, e.g., through exposure to ultra-violet rays. The layers of layer stack may be formed using any of a number of suitable and known deposition processes, including chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and physical vapor deposition (PVD) such as sputtering.
To form the aforementioned metallic interconnect lines, a portion of the layers of the layer stack, including the metallization layer are etched using a suitable photoresist technique. By way of example, one such photoresist technique involves the patterning of the photoresist layer by exposing the photoresist material in a contact or stepper lithography system, and the development of the photoresist material to form a mask to facilitate subsequent etching. Using an appropriate etchant, the areas of the metallization layer that are unprotected by the mask are then etched away, leaving behind metallization interconnect lines or features.
To achieve greater circuit density, modern IC circuits are scaled with increasingly narrower design rules. As a result, the feature sizes, i.e., the width of the interconnect lines or the spacings (e.g., trenches) between adjacent interconnect lines, have steadily decreased.
As the feature sizes shrink, it becomes increasingly difficult to achieve a good quality resist pattern with enough resist thickness due to the limits of current lithography technology. This demands processes with higher selectivity to resist to ensure transfer quality of the pattern to the layers underneath.
As the feature sizes shrink, it becomes increasingly difficult to achieve a uniform etch rate across the wafer. Typically, the etch rate in the narrow spacings is slower than that in wider trenches or open field regions. This phenomenon, referred herein as the loading in etch rates, may be a consequence of microloading and/or aspect ratio dependent etching (ARDE). Microloading refers primarily to the situation wherein the etch rate is smaller in areas where there is a high density of line spacings relative to the etch rate of identically sized trenches located in a less dense area. ARDE, on the other hand, refers primarily to the situation wherein variations in etch rates are observed among trenches that are located in areas of similar trench density and among trenches that have different aspect ratios. The loading in etch rates causes trenches to be formed in the layer stack at different rates. As a result of the etch rate variations, by the time metal etching is complete in areas having a slow etch rate (e.g., in the narrower line spacings), overetching, i.e., the inadvertent removal of materials from underlying layers, may have already occurred in areas having a higher etch rate (e.g., the open field regions).